1. Field of the Invention
The present invention relates to an architecture for a phase-locked loop (PLL) circuit. More specifically, the present invention relates to a PLL circuit that compensates for the distribution delay experienced by a clock signal as it is routed through a programmable logic device, such as a field programmable gate array (FPGA).
2. Related Art
FIG. 1 is a block diagram of a conventional phase-locked loop (PLL) circuit 100. PLL circuit 100 includes voltage controlled oscillator (VCO) 101, phase comparator 102 and loop filter 103. VCO 101 generates an output clock signal, VCO.sub.OUT, in response to a frequency control voltage provided by loop filter 103. VCO 101 is an analog device which is designed to generate a VCO.sub.OUT signal having a frequency which is controllable within a range about a desired frequency. The VCO.sub.OUT signal is provided to phase comparator 102. Phase comparator 102 is also coupled to receive a reference clock signal CLK.sub.REF. Phase comparator 102 determines the phase difference between the VCO.sub.OUT and CLK.sub.REF signals, and in response, generates an error signal (ERROR) which is representative of this phase difference. Loop filter 103 integrates the ERROR signal, thereby creating the frequency control voltage. The frequency control voltage, in turn, controls the frequency of the VCO.sub.OUT signal generated by VCO 101.
If the VCO.sub.OUT signal lags in phase with respect to the CLK.sub.REF signal, then phase comparator 102 generates an ERROR signal having a first logic level (e.g., V.sub.CC). Loop filter 103 integrates this ERROR signal to create the frequency control voltage. This frequency control voltage, when applied to VCO 101, causes the frequency of the VCO.sub.OUT signal to increase, thereby causing the VCO.sub.OUT signal to gain in phase with respect to the CLK.sub.REF signal.
Similarly, if the VCO.sub.OUT signal leads in phase with respect to the CLK.sub.REF signal, then phase comparator 102 generates an ERROR signal having a second logic level (e.g., V.sub.SS). Loop filter 103 integrates this ERROR signal to create the frequency control voltage. This frequency control voltage, when applied to VCO 101, causes the frequency of the VCO.sub.OUT signal to decrease, thereby causing the CLK.sub.REF signal to gain in phase with respect to the VCO.sub.OUT signal.
In the foregoing manner, PLL circuit 100 continuously adjusts the frequency of the VCO.sub.OUT signal to eliminate any phase difference between the CLK.sub.REF and VCO.sub.OUT signals. The operating parameters of VCO 101, phase comparator 102 and loop filter 103 are selected to provide a stable closed loop control system. As a result, PLL circuit 100 ultimately eliminates the phase difference between the VCO.sub.OUT and CLK signals. At this time, the VCO.sub.OUT and CL.sub.REF signals will be matched in both frequency and phase (i.e., synchronized). Under these conditions, PLL circuit 100 is said to be "locked". PLL circuit 100 remains locked by continual small adjustments of VCO 101 based on the feedback received from phase comparator 102 and loop filter 103.
One application of PLL circuit 100 is to compensate for clock distribution delays which occur within application specific integrated circuits (ASICs).
FIG. 2 is a block diagram of a conventional ASIC 200 which operates in response to an input clock signal CLK.sub.IN. The CLK.sub.IN signal is routed through an input buffer circuit 201 to internal circuitry 202 of the ASIC. While traveling through internal circuitry 202, the CLK.sub.IN signal experiences a clock distribution delay (t.sub.dd) thereby resulting in a distributed clock signal DIST.sub.-- CLK. The DIST.sub.-- CLK signal clocks data values D.sub.IN through output register 203 as output data values D.sub.OUT. A clock-to-out delay (t.sub.co) exists from the time the DIST.sub.-- CLK signal is applied to output register 203 until the time that a corresponding data value D.sub.OUT is provided out of output register 203.
FIG. 3 is a waveform diagram illustrating CLK.sub.IN signal 301, DIST.sub.-- CLK signal 302 and D.sub.OUT signal 303, as well as the clock distribution delay t.sub.dd and the clock-to-out delay, t.sub.co. As illustrated in FIG. 3, the clock distribution delay, t.sub.dd and the clock-to-out delay t.sub.co are cumulative, such that the total delay (t.sub.total) from the time that the CLK.sub.IN signal is received until the time that the data value D.sub.OUT is output is equal to t.sub.dd plus t.sub.co.
In order to reduce the total delay t.sub.total, certain ASICs, such as ASIC 200, have implemented an on-chip PLL circuit in the manner illustrated in FIG. 4. In this circuit, VCO 101 provides the VCO.sub.OUT signal to internal circuitry 202. The VCO.sub.OUT signal undergoes the previously described clock distribution delay t.sub.dd, thereby creating the distributed clock signal, DIST.sub.-- CLK. The DIST.sub.-- CLK signal is used to clock data values D.sub.OUT out of output register 203.
The DIST.sub.-- CLK signal is also provided to an input terminal of phase comparator 102. The other input terminal of phase comparator 102 is coupled to receive the CLK.sub.IN signal from input buffer 201. In response, phase comparator 102 generates an ERROR signal that is representative of the phase difference between the CLK.sub.IN and DIST.sub.-- CLK signals. This ERROR signal is integrated by loop filter 103 to create the frequency control voltage. The frequency control voltage, in turn, controls the frequency of the VCO.sub.OUT signal generated by VCO 101. The VCO.sub.OUT signal is controlled such that the DIST.sub.-- CLK signal becomes synchronized with the CLK.sub.IN signal.
FIG. 5 is a waveform diagram illustrating CLK.sub.IN signal 501, VCO.sub.OUT signal 502, DIST.sub.-- CLK signal 503 and D.sub.OUT signal 504 as generated within ASIC 200 of FIG. 4. As previously stated, the PLL circuitry causes DIST.sub.-- CLK signal 503 to be synchronized with CLK.sub.IN signal 501. As a result, the total delay t.sub.total from the time that the CLK.sub.IN signal 501 is received until the data value D.sub.OUT is output is equal to the clock-to-out time t.sub.co of output register 203. The clock distribution delay t.sub.dd is effectively hidden by causing the VCO.sub.OUT signal 502 to lead the DIST.sub.-- CLK signal 503 by a time period which is exactly equal to the clock distribution delay t.sub.dd.
It is possible to implement a PLL circuit on ASIC 200 because the desired operating frequency of ASIC 200 is well defined. The operating frequency of ASIC 200 is selected during the design of the ASIC. VCO 101, phase comparator 102 and loop filter 103 are designed to operate at this predetermined operating frequency. For example, ASIC 200 may be designed to operate at 100 MHz. In such an example, VCO 101 might generate a VCO.sub.OUT signal which varies between 90 and 110 MHz (i.e., 100 MHz +/-10 percent). The operating frequency of ASIC 200 could not subsequently be changed to 50 MHz because VCO 101 is not capable of generating an appropriate VCO.sub.OUT clock signal.
Field programmable gate arrays (FPGAs) are programmable logic devices that can be configured to perform different logic functions. The operating frequency of an FPGA is not limited in the same manner as the operating frequency of an ASIC. That is, an FPGA is a digital circuit that is designed to be operated in response to many different input clock frequencies. Because PLL circuits are limited to operating within a relatively narrow range of frequencies, it is not practical to implement a PLL circuit on the same chip as an FPGA. Implementing a PLL circuit on an FPGA would undesirably limit the operating frequency of the FPGA to the operating frequency of the PLL circuit.
An alternative would be to include a mechanism on the FPGA to modify the operating frequency of the PLL circuit. However, the programmable mechanisms available in an FPGA are digital in nature. As a result, selected circuit elements would have to be either connected or disconnected using transistor switches to configure different PLL circuits when the FPGA is operated at different frequencies. This method of digital configuration is inappropriate for making the fine adjustments required to modify the operating frequency of a PLL circuit.
For the foregoing reasons, PLL circuits have not typically been implemented on the same chips as FPGAs.
In the instances where PLL circuits have been used with FPGAs, the entire PLL circuit (i.e., VCO 101, phase comparator 102 and loop filter 103) has been located on a chip which is separate from the FPGA chip. However, the delays resulting from transmitting the various signals across the FPGA chip interface cause a loss in performance.
It would therefore be desirable to have an improved method and structure for operably coupling a PLL circuit with an FPGA.